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Wireless Components
FM Car Radio IC with PLL TUA 4401K V 2.1
Specification 17.02.00
DS 1
Revision History: Current Version: 02.00 Previous Version:Data Sheet 23.09.1999 Page (in previous Version) 3-7 3-11 5-3 5-5 5-5 5-5 Page (in current Version) 3-7 3-11 5-3 5-5 5-5 5-5 Subjects (major changes since last revision)
Functional description pin 41 corrected Functional description pin 41 corrected Sequence tests 310 to 317 changed (Item) Values attack current changed Values recovery current changed Values detector characteristic changed
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1.
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TUA 4401K
Productinfo
Productinfo
General Description Package The TUA 4401K is the first Infineon Carradio IC using BICMOS technology. The combination of an analog FM receiver circuit and a digital PLL synthesizer on the same chip reduces the over all pin count in comparison to two separate IC's and in addition the number of necessary external components. This gives the flexibility both for high performance and low cost applications. The recommended applications for this device are FM only carradios and background receivers, capable for all world standards. Double balanced RF mixer with low noise figure, high IP3 and wide dynamic range Strictly symmetrical RF circuitry IF amplifier with adjustable gain Double frequency 1st LO option 7 stage limiter amplifier with dB linear fieldstrength output Low distortion coincidence demodulator Multipath detector with analog output FM only car radio receiver, background receiver CMOS PLL-Synthesizer Resolution between 100 kHz and 6.25kHz Search tuning stop with IF counter and Fieldstrength/Multipath evaluation ADC's for fieldstr. and multipath detector I2C Bus operation
Ordering Information
Type TUA 4401K Ordering Code Package MQFP-44
Wireless Components
Applications
Product Info

Features
Specification, 17.02.00
1
Table of Contents
1 Table of Contents 1-1
2 Product Description 2.1 2.2 2.3 2.4 General Description Applications Features Package Outlines
2-1 2-2 2-3 2-3 2-4
3 Functional Description 3.1 3.2 3.3 3.4 Pin Configuration Block Diagram Functional Block Diagram Circuit Description
3-1 3-2 3-12 3-13 3-14
4 Applications 4.1 Application and Circuits
4-1 4-2
5 Reference 5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 Electrical Data Absolute Maximum Range Operating Range AC/DC Characteristics Phase detector outputs Bus Interface I2C Bus Timing
5-1 5-2 5-2 5-2 5-3 5-7 5-8 5-13
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
TUA 4401K
Product Description
2.1 General Description
The TUA 4401K is the first Infineon Carradio IC using BICMOS technology. The combination of an analog FM receiver circuit and a digital PLL synthesizer on the same chip reduces the over all pin count in comparison to two separate IC's and in addition the number of necessary external components. This gives the flexibility both for high performance and low cost applications. The recommended applications for this device are FM only carradios and background receivers, capable for all world standards.
TUA 4401K features: Frontend High level, high impedance mixer input with improved dynamic range High input / output 3rd order intercept point Integrated prestage AGC generation and control for PIN diodes and MOS tetrode Bus controlled AGC threshold 2 pin 1st local oscillator with improved low phase noise, internally coupled to PLL. Double frequency operation possible Strictly symmetrical RF parts PLL with fast acquisition mode Resolution 100 kHz, 50 kHz, 25 kHz, 12,5 kHz, 10 kHz and 6.25 kHz High running (61.5 MHz) crystal oscillator to avoid interference with bus controlled adjustment
IF amplification, demodulation and STS Low noise IF amplifier Gain adjust with DC control voltage or serial bus possible 7 stage IF limiter with extended fieldstrength range suitable for the IF frequency range of 10.7 MHz ... 21.4 MHz Fieldstrength DC output and ADC output available Low distortion coincidence demodulator (using short loop AFC principle) with MPX output Wideband multipath detector with analog output and ADC output IF counter for search tuning stop with selectable IF center frequency, window width and programmable thresholds for fieldstrength and multipath evaluation STS informations -in window-,-below-,-beyond- available
Wireless Components

2-2
Specification, 17.02.00
TUA 4401K
Product Description
I2C Bus I2C bus (2 wire, fast mode device with 400 kbit/s) operation possible Bus interface with low threshold voltage Schmitt Trigger inputs for interfacing 3V or 5V microprocessors
2.2 Applications
2.3 Features
Wireless Components

FM only car radio receiver, background receiver
Double balanced RF mixer with low noise figure, high IP3 and wide dynamic range Strictly symmetrical RF circuitry Double frequency 1st LO option IF amplifier with adjustable gain 7 stage limiter amplifier with dB linear fieldstrength output Low distortion coincidence demodulator Multipath detector with analog output CMOS PLL-Synthesizer Resolution between 100 kHz and 6.25kHz Search tuning stop with IF counter and Fieldstrength/Multipath evaluation ADC's for fieldstr. and multipath detector I2C Bus operation
2-3
Specification, 17.02.00
TUA 4401K
Product Description
2.4 Package Outlines
MQFP 44
Wireless Components
2-4
Specification, 17.02.00
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
TUA 4401K
Functional Description
3.1 Pin Configuration
AGCOUT_P
IFOUTFM
VREFRF
IFAMPC
GNDIF1
IFINFM
VCCIF
33 F M IF IN 34
32
31
30
29
28
27
26
25
24
23 22 FM 1
F M IB IAS
35
FM2
IFIN
IF1
IF2
21
PR E _C A P
G N D IF 2
36
20
VC C R F
M PXOUT
37
19
OSC2
FSOUT
38
18
OSC1
M P A_ IN
39
M Q F P 44
17
GNDRF
M P AC AP
40
16
PD _ 0
M P A _O U T
41
15
PD A
D E M AF C
42
14
PO R T _ 1
PH02
43
13
GNDD
PH01
44 1 FS_ADC 2 MPA_ADC 3 Station_Detect 4 SCL 5 SDA 6 VREFD5V 7 VREFD3V 8 XTAL_DIV6 9 PORT_2 10 QUARTZ1 11 QUARTZ2
12
VC C D
Pin_config.wmf
Figure 3-1
IC Pin Configuration
Table 3-1 Pin Configuration Pin No. Symbol Equivalent I/O-Schematic Function
+5V
1
1
FS_ADC
1: ADC input fieldstrength
+5V 5 pF
2
MPA_ADC
2
GNDD
2: ADC input multipath detector
Wireless Components
3-2
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued) Pin No. Symbol Equivalent I/O-Schematic Function
+ 5V
3
Station_Detect
3
3: IF counter output station detector
GNDD
+ 5V
4
SCL
4
330
+5V GNDD
4: I2C bus clock input
+ 5V
5
330
5
SDA
5: I2C bus data in/output
GNDD
6
VREFD5V
6: Reference voltage digital section (5V) 7: Reference voltage digital section (3V)
7
VREFD3V
V+ 3V
8
XTAL_DIV6
2k 8
8: Crystal oscillator auxiliary output (10.25 MHz)
2 0 0 fF
GNDD
Wireless Components
3-3
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued) Pin No. Symbol Equivalent I/O-Schematic Function
+5V
9
PORT_2
330
9
9: Switch port output 2(open drain)
GNDD
+V 10
10
QUARTZ1
2,5 k
10: Reference oscillator input / Crystal
11
5k
5k
11
QUARTZ2
11: Reference oscillator input / Crystal
12
VCCD
12: Positive power supply voltage for serial bus and synthesizer 13: Ground for serial bus and synthesizer
13
GNDD
14
PORT_1
330
+5V
14
14: Switch port output 1 (open drain)
GNDD
Wireless Components
3-4
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued) Pin No. Symbol Equivalent I/O-Schematic Function
VCCD
+5 V
IPDA
15
15
PDA
15: PLL phasedetector output analog (Tuningvoltage)
3k
PD
GNDD
+5 V
12
PD
+5 V
16
16
PD_0
16: PLL chargepump output (Phase detector tristate chargepump output)
+5 V
NC
17
GNDRF
17: Ground for RF part
Wireless Components
3-5
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued) Pin No. Symbol Equivalent I/O-Schematic Function
+V
+V
18
OSC1
18
19
18: 1st local oscillator circuit
19
OSC2
19: 1st local oscillator circuit
2 ,2 V
20
VCCRF
20: Positive power supply voltage for RF part
+V
21
21
PRE_CAP
6 ,4 V
21: Prestage AGC time constant capacitor; output for MOS tetrode gate 2
Wireless Components
3-6
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued) Pin No. Symbol Equivalent I/O-Schematic Function
22
FM1
+V
25
26
22: FM 1st mixer symmetrical input
22
23
FM2
23 2,0k 2,0k
23: FM 1st mixer symmetrical input
2 ,6 V
24
+V
24
AGCOUT_P
24: Prestage AGC current output for PIN diode normal polarity
Wireless Components
3-7
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued) Pin No. Symbol Equivalent I/O-Schematic Function
25
26
25
IF2
+V
25: 1st mixer output (open collector)
22
26
IF1
23
2,0k 2,0k
26: 1st mixer output (open collector)
2 ,6 V
27
VREFRF
27: Reference voltage RF section (4.8V) 28: Ground for IF amplifier
28
GNDIF1
+V
29
IFINFM
30
29: 10.7 MHz IF amplifier input
330
29
30
IFIN
30: 10.7 MHz IF amplifier operation point
17k
3 ,8 V
Wireless Components
3-8
17k
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued) Pin No. Symbol Equivalent I/O-Schematic Function
+V 330 31
31
IFOUTFM
31: 10.7 MHz IF amplifier output
+V 32
32
IFAMPC
33
VCCIF
8k
32: 10.7 MHz IF amplifier DC gain control adjust blocking capacitor
33: Positive power supply voltage for IF amplifier
+V 35
34
FMIFIN
330
34: FM limiter input
34
33k
33k
35
FMIFBIAS
5 ,5 V
35: FM limiter input bias decoupling capacitor
36
GNDIF2
36: Ground for limiter amplifier
Wireless Components
3-9
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued) Pin No. Symbol Equivalent I/O-Schematic Function
+V 37
37
MPXOUT
37: FM MPX signal output
+V
38
NC
+V
38
FSOUT
38: Fieldstrength output
34k
66k
+V 86k
39
MPA_IN
39
39: Multipath detector input
Wireless Components
3 - 10
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued) Pin No. Symbol Equivalent I/O-Schematic Function
40
+V
40
MPACAP
40: Multipath detector rectifier capacitor
41
MPA_OUT
+V
41: Multipath detector output
41
+V
42
DEMAFC
76k
42
42: Demodulator AFC blocking capacitor
3 ,5 V
+V
43
PH02
15p
43: Demodulator circuit
15k
4 3 /4 4
44
PH01
4 ,8 V
44: Demodulator circuit
Wireless Components
3 - 11
Specification, 17.02.00
TUA 4401K
Functional Description
3.2 Block Diagram
IFAMPC
AGC_OUT_P
IFOUTFM
VREFRF
GNDIF1
IFINFM
VCCIF
33 F M IF IN 34
32
31
30
29
28
27 V re f
26
25
24
23 22 FM 1
IF A M P F M IF B IA S 35
FM2
IFIN
IF1
IF2
21
PRE_CAP
G N D IF 2
36 F M L im / D e m / F S / M P -D e t M ixe r 1 st L O P re se t A G C
20
VCCRF
M PXOUT
37
19
OSC2
FSOUT
38
18
OSC1
M P A _ A IN
39
17
GNDRF
M PACAP
40 P L L S yn th . S e ria l B u s IF co u n te r A D C /D A C
16
PD_0
M PA_O UT
41
15
PDA
DEM AFC
42
14
PO RT_1
PH02
43
13 C ryst O SC 1 2 10 11 QUARTZ1 QUARTZ2
GNDD
PH01
44 1 FS_ADC 2 MPA_ADC 3 Station_Detect 4 SCL 5 SDA 6 VREFD5V 7 VREFD3V 8 XTAL_DIV6 9 PORT_2
VCCD
Funct_block.wmf
Figure 3-2
Main Block Diagram
Wireless Components
3 - 12
Specification, 17.02.00
VCC IF
Figure 3-3
10.7 MHz CER Filter 10.7 MHz CER Filter 37 FM IF limiter AfC loop Dem 25 26 or Amp 29 31 34 IF amp gain adj.
30
32
28
10.7 MHz 35 CER Filter
33
36
44
43
42
MPX out
39
22
MOS tetrode
FM
23
VCC RF
20
OSC Buffer / 2 bit DAC Prest. AGC thresh. 4 bit DAC IF gain VRef IF Field strength
3.3 Functional Block Diagram
SCL
P1
P2
SDA
VCCD
Station_Detect
Functional Block Diagram
3 - 13
N counter PD R counter Gate time counter Data Bus SOCCAR Bus Port adj crystal Charge pump div/6 Clock counter 4 5 15 16 14 9 10 11 8 12 6 7
Div 2
18
OSC
MP det in
Wireless Components
External 40 MP det. 41 38 MP det out Fieldstrength IF counter 7 Bit ADC 2 1 3 13
Gate2
21
FM
Pin Diode 1
24
prest
AGC
19
1. LO
27
VREF RF
17
TUA 4401K
Functional Description
Funct_block.wmf
Specification, 17.02.00
TUA 4401K
Functional Description
3.4 Circuit Description
The TUA 4401K is a one chip FM car radio system consisting of RF frontend, gain adjustable IF amplifier, FM-IF limiter amplifier, demodulator, PLL synthesizer, IF counter for STS and ADC's for fieldstrength and multipath detector. The serial bus is a I2C type. 1. FM frontend The frontend consists of a two pin varactor tuned oscillator, a double balanced mixer and a prestage AGC control circuit. The mixer has an improved intermodulation behaviour and converts the RF signal to the 10,7 MHz IF range . Two inputs allow both symmetrical and unsymmetrical operation. The integrated AGC stage for prestage control drives MOSFETS as well as PIN diodes a with cur- rent driver. The AGC threshold can be set with a serial bus controlled 2 Bit DAC. For background receiver application the oscillator is able run at double frequency, a subsequent frequency divider by 2 is activated by serial bus to provide the correct mixer frequency. 2. FM IF amplifier After the mixer an IF amplifier is present for IF post amplification. Input and output impedance are both 330 Ohms for matching with ceramic filters. For adjusting the over all gain the IF amplifier gain can be adjusted with a serial bus controlled 4 Bit DAC. 3. FM limiter and demodulator The FM IF amplifier includes a seven stage capacitive coupled limiter amplifier and a fieldstrength generator with high linearity and increased dynamic range. The coincidence demodulator has an additional AFC short loop circuit with integrated varactor diode in parallel to the external tank circuit to improve the distortion bahaviour in case of detuning. 4. Multipath detector A wideband multipath detector with analog output is available. 5. A/D converter for fieldstrength and multipath detector The 7 bit A/D converter has two input channels and works as successive approximation converter. The conversion time for both input signals is t = 32 s. The 7-bit digital-words from both channels (14 bit) are read out together via bus into two bytes with the read subaddress 82H. The input voltage range for both channels is 0...VREFD5V. 6. IF counter and multipath/fieldstrength evaluation for STS FM center frequencies ar available in two ranges set by bit D7 in subaddress 05H. For D7=1 the range of centerfrequency is 20.800 MHz...22.3875 MHz in 128 steps (12.5 kHz per step). For D7=0 the range of centerfrequency is 10.400 MHz...11.1937 MHz in 128 steps (6.25 kHz per step). The gate time is adjustable in 8 steps from 320us...40.96ms and the tolerance of the accepted count value, the window is adjustable in 5 steps from +/- (6.25kHz...100kHz) for D7=0 in sub-address 05H and
Wireless Components
3 - 14
Specification, 17.02.00
TUA 4401K
Functional Description
+/- (12.5 kHz...200 kHz) for D7=1 in subaddress 05H. The results IF_CENT and IF_WINDOW are read out via bus (read-subaddress 82H&83H) or pin Station_Detect. If the IF frequency is into the preselected window, Station_Detect goes from high to low level. If the IF frequency is outside the preselected window, Station_Detect is high. The bit IF_WINDOW is a hint IF-frequency that is to low (IF_WINDOW=high) or is to high (IF_WINDOW=low). In addition to the frequency measurement, thresholds for multipath and fieldstrength voltages can be programmed via bus (subaddress 0BH). Station_Detect will only go to low level in case of field-strength and multipath voltages are beyond the thresholds and the frequency is inside the window. When setting the thresholds to zero multipath and fieldstrength evaluation is disabled. 7. Crystal oscillator A master crystal oscillator provides all necessary clock frequencies for the whole IC. A 61.5 MHz crystal is used in 3rd harmonic mode. The oscillator frequency can fine tuned with a serial bus controlled 4 bit D/A converter. The crystal frequency is used as reference frequency for the PLL oscillator and IF counter. It is also used as clock for the ADC's. Finally the crystal frequency divided by 6 (10.25 MHz) is available at a pin as low pass filtered voltage, it can be disabled with the serial bus. 8. Output ports PORT_1 / 2 are NMOS Open drain outputs. 9. I2C Bus The TUA4401K supports the I2C bus protocol (2 wire). All bus pins ( SCL, SDA) are Schmitt triggered input buffer for 3V or 5V C. The bit stream begins with the most significant bit (MSB), is shifted in (write mode) on the low to high transition of CLK and is shifted out (read mode) on the high to low transition of CLK I2C bus mode: Data Transition: Data transition on the pin SDA must only occur when the clock SCL is low. SDA transitions while SCL is high will be interpreted as start or stop condition. Start Condition (STA): A start condition is defined by a high to low transition of the SDA line while SCL is at a stable high level.This start condition must precede any command and initiate a data transfer onto the bus. Stop Condition (STO): A stop condition is defined by a low to high transition of the SDA while the SCL line is at a stable high level. This condition terminate the communication between the devices and forces the bus interface into the initial conditions.
Wireless Components
3 - 15
Specification, 17.02.00
TUA 4401K
Functional Description
Acknowledge (ACK): Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has receive the 8 bits of data correctly. Data Transfer Write Mode: To start the communication, the bus master must initiate a start condition, followed by the 8bit chip address (write). The chip address for the TUA 4401 is fixed as "1100110" (MSB at first). The last bit (LSB=A0) of the chip address byte defines the type of operation to be performed: A0=1, a read operation is selected and A0=0, a write operation is selected. After this comparison the TUA 4401 will generate an ACK. After this device addressing the desired subaddress byte and data bytes must be followed. The subaddresses determines which one of the 9 data bytes (00H...07H, 0BH) is transmitted first. At the end of data transition the master must be generate the stop condition. Data Transfer Read Mode: To start the communication in the read mode, the bus master must initiate a start condition, followed by the 8bit chip address (write: A0=0), followed by the sub address read (82H/83H), followed by the chip address (read: A0=1). After that procedure the 16bit/8bit data register 82H/83H is read out. After the first 8 bit read out, the uP mandatory send LOW during the ACK-clock. After the second 8 bit read out the uP mandatory send HIGH during the ACK-clock. At the end of data transition the master must be generate the stop condition. 10.PLL Synthesizer R / N Counter The TUA 4401K has 2 identical 16bit counter for R and N path. Input frequency for the R-counter is the buffered XTAL-frequency (61.5MHz). Tuning steps can be selected by the 16bit R-counter from fR= 6.25kHz...100kHz. Input frequency for the N-counter is the buffered LO-frequency (in FM mode 98.2MHz...118.7MHz). Three State Phase Comparator The phase comparator generates a phase error signal according to phase difference between fR (R counter output) and fN (N counter output).This phase error signal drives the charge pump current generator. Charge Pump The charge pump generates signed pulses of current. 4 current values are available. Loop Amp The integrated rail to rail loop amplifier allows an active loop filter design with external components. Two modes are available with status bit D11: high speed and normal mode.
Wireless Components
3 - 16
Specification, 17.02.00
4
Applications
Contents of this Chapter 4.1 Application and Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
1k
3,3k
3,3k
1k 1uH 10n 1n 4,7k 22k 10uH
+ 22k
10k
33k
BB914 10k 61.5MHz 22n 33n 1n 1n 33n 22n 6,8n 10n 1n
1
SDA VccD PD PD_0 Vref5V Port1 R-counter local oscill Vref3V Xtal/6 Port2 N-counter
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
BAR63
20
VccRF
100
21
PreCap
22
FM1
Test Circuit
FS_ADC
MPA_ADC
IF-CENT
SCL
4.1 Application and Circuits
10n
51
100
1k
22n
100
1k
1k
1k
4,7k
330
100
100uH
51
51
TOKO 600BNS-A1004HM +
1n
1k
+
330
FM only car radio receiver, background receiver
-
10
4-2
TUA4401K
MDP-Cap MDP-in MPX-out IFin FMIFbias FMIFin VccIF Fieldstrength IFampC IFout_FM IFinFM VrefRF
DemAFC
MPD-out
MIX1
MIX2
AGCout_p
FM2
44
22n 10n 47n 22n 22n 22n 22n 22n
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
33n
27
26
25
24
23
68p
1uF
1n TOKO 218FCS-2166N 51
3,3k
200kHz audio measure system
RF-source 10.7MHz
RF-measure 10.7MHz
RF-source 10.7MHz
RF-measure 10.7MHz
RF-source 110.7MHz
1k
Figure 4-1
150p
Wireless Components
I2C-Bus RF-source time measurement time measurement time measurement
ramp
TUA 4401K
Applications
4401K_Test_circ.wmf
Specification, 17.02.00
TUA 4401K
Applications
4401K_SPEC.eps
Figure 4-2
Application Circuit
Wireless Components
4-3
Specification, 17.02.00
5
Reference
Contents of this Chapter 5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 I2C Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
TUA 4401K
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Range
The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Range Parameter Symbol Limit Values min max Unit
ESD-Protection all bipolar pins HBM ( R=1.5k , C=100pF ) ESD-Protection all CMOS pins HBM ( R=1.5k , C=100pF ) Total power dissipation Ambient temperature Junction temperature Storage temperature Thermal resistance P-MQFP-44 (sys-air)
VESD VESD Ptot TA Tj Tstg TthSA
-1 -1
1 1 900
kV kV mW C C C K/W
- 40
85 150
- 40
125 65
All values are referred to ground (pin), unless stated otherwise. All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from Vs across the designated pin), it has a positive sign.
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Ratings Parameter Symbol Limit Values min max Unit Test Conditions L Item
Supply voltage Current consumption Ambient temperature
VVCC Ivcc TA
8
9 111
V mA C
- 40
85
Wireless Components
5-2
Specification, 17.02.00
TUA 4401K
Reference
5.1.3
AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 8.5 V Symbol min Power Supply Limit Values typ max Unit Test Conditions L Item
Total current consumption
1st local oscillator Frequency range Frequency range Frequency range Negative input impedance RF mixer Mixer current Input frequency Max input RF level Input impedance single ended Mixer gain Input IP3 Noise Figure Reference voltage RF section Prestage AGC outputs AGC threshold range AGC threshold range AGC threshold range AGC threshold range AGC voltage for MOSFET Gate 2 AGC voltage for MOSFET Gate 2 AGC current normal polarity
IVCC
85
111
mA
f1st LO f1st LO f1st LO Z18-19
50 50 160
- 1000
250 150 250
MHz MHz MHz Q factor of coil > 90 coil tbf; see SUB06h f = 100 MHz L
Imix
11 60 120
14
17 140
mA MHz dBV
101
f22-23 V22-23 R22-23 C22-23 Amix
1.8 2.5 12 15 126 18
k pF dB dBV dB 5.3 V IM = 60 dB
L L
259 L L 104
F V27 4.3
6 4.8
V22-23 V22-23 V22-23 V22-23 V21 V21 I24
48 36 24 10 5.7
60 45 30 15 6.4
72 54 36 20
mV mV mV mV V
see diagram SUB06h see diagram SUB06h see diagram SUB06h see diagram SUB06h V22-23 = 0 mV V22-23 = 200 mV V22-23 = 0 mV
310 311 312 313 314 315 316 317 106 300 115
0.1 10 13
V mA
Wireless Components
5-3
Specification, 17.02.00
TUA 4401K
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 8.5 V (continued) Symbol min AGC current normal polarity Integrator current Integrator current I24 I21 I21 -75 25 -50 50 Limit Values typ max 0.1 -25 75 mA A A V22-23 = 200 mV V22-23 = 0 mV; Vm = 3V V22-23 = 200 mV; Vm = 3V 301 117 303 Unit Test Conditions L Item
IF amplifier DC input voltage Input resistance Output resistance Max. Voltage gain Min. Voltage gain Noise figure V29 R29 R31 A31-29 A31-29 F 23 10 3.4 3.7 330 330 26 13 7 29 16 4.0 V dB dB dB see diagram SUB07h see diagram SUB07h RG = 330
L
108
L 403 405
IF limiter amplifier / fieldstrength generator Input voltage for limiter threshold AM suppression Fieldstrength voltage Fieldstrength voltage Fieldstrength voltage Fieldstrength voltage Fieldstrength dynamic range Fieldstrength linearity Fieldstrength temperature drift FM demodulator AF output voltage AF output voltage Total harmonic distortion Total harmonic distortion detuned V37 V37 THD37 THD37 500 600 300 0.3 0.6 0.8 720 mVrm
s
V34 AAM V38 V38 V38 V38 V38dyn V38lin V38temp 1.5 2.4 3.6 70
25 80 0.4 1.9 2.9 4.2 90 1
45
Vrm
s
fin = 10.7 MHz; V37 - 3 dB m = 30 %, V34=100mV V34 = 0 mVrms V34 = 1 mVrms V34 = 10 mVrms V34 = 200 mVrms
470 469 450 451 452 471
dB 0.8 2.3 3.4 4.8 V V V V dB dB 3 dB
F = 75 kHz; fIF=10.7 MHz F = 75 kHz; fIF= 21.4 MHz F = 75 kHz fin = 10.7 MHz 50 kHz; F = 75 kHz L
455
mVrm
s
% %
456 457
Wireless Components
5-4
Specification, 17.02.00
TUA 4401K
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 8.5 V (continued) Symbol min Multipath detector Attack current Recovery current Start voltage Detector characteristic I40*) I40*) V41Def V41
V41Def -3.1 V
Limit Values typ max
Unit
Test Conditions
L
Item
700 -8
900 -13 4.7
V41Def -2.8 V
1200 -18
A A V
V39 = 350 mVrms; Vm = 5 V V39= 0 Vrms; Vm = 3.6 V V39 = 0 Vrms f39 = 200 kHz V39 = 40 mVrms
801 802 114 800
V41Def -2.5 V
V
*) Detector currents are measured between the output pin (-pole) and a voltage source Vm Crystal oscillator Operating frequency Negative input impedance Negative input impedance Input impedance crystal Spurious harmonics crystal Bus controlled adjust range Bus controlled output XTAL_DIV6 Bus controlled output XTAL_DIV6 Bus controlled output XTAL_DIV6 f10-11 Z10-11 Z10-11 Rcr asp fadj VXTAL_DIV6 on AC VXTAL_DIV6 on DC VXTAL_DIV6 off DC 1.0 40 500 1.5 2.0 50 61.5 - 250 1.4 70 - 20 MHz k dB ppm mVpp VDC
mVDC
3rd harmonic f = 61.5 MHz f = 20.5 MHz 3rd harmonic f < 200 MHz see diagram SUB06h f = 10.25 MHz, Cload = 10 pF f = 10.25 MHz, Cload = 10 pF Cload = 10 pF 180 197
Chargepump output (Loopfilter input) DC voltage DC current DC current DC current DC current Tristate output current VPD_0 IPD_03 IPD_02 IPD_01 IPD_00 IPD_0OFF 2.3 3.2 1.6 0.8 400 2.5 4 2 1 500 0.1 2.7 5.2 2.6 1.3 700 10 V mA mA mA uA nA VPD_0 = 2.5V , guaranteed by design 228 locked see Status, Subaddress 00H, bit D1, D2 VPD_0 = 2.5V 251 252 220 to 227
Loop amplifier tuningvoltage output (Loopfilter output) LOW output voltage HIGH output voltage VPDA_L VPDA_H 0 VVCC -0.5V 400 VCC mV mV ITUNE = 100 uA ITUNE = -100 uA 231 230
Wireless Components
5-5
Specification, 17.02.00
TUA 4401K
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 8.5 V (continued) Symbol min HIGH output current source LOW output current source IPDA_H IPDA_L -1.9 -0.9 Limit Values typ -2.4 -1.2 max -2.9 -1.5 mA mA VTUNE = 4V, VPD_0 = 0V (see Status, Subaddress 00H, bit D11) 232 Unit Test Conditions L Item
233
PLL for synthesizer (see PLL Synthesizer on page 3-16) PLL / VCO step size (programmable via Rcounter) N-counter divide ratio fref 6.25 100 kHz f crystal = 61.5 MHz
N
2
65535
16-Bit
200 to 207 210 to 216
R-counter divide ratio
R
2
65535
16-Bit
Port outputs, PORT_1, PORT_2, IF_CENT, IF_WINDOW (see Output ports on page 3-15) LOW output voltage HIGH Leakage current VP IP_LEACK 0 0 100 400 100 mV nA IP = 1 mA VP = 5 V *1) *2)
*1) 830, 840, 831, 834 *2) 118, 119, 124, 125 I2C bus (SCL, SDA) (see I2C Bus Timing on page 5-12 and Bus Data Format on page 3-15) H-input voltage L-input voltage Hysteresis of Schmitt trigger inputs (SCL, SDA) Input capacity I2C bus leakage current VIH VIL Vhys CI I_LEACK 0 2.10 -0.5 0.30 5 1 5.50 0.90 V V V pF A Values only valid for applied VCC L 150 150
Ref voltages Ref voltage Ref voltage V6 V7 4.5 2.7 5.0 3.0 5.5 3.3 V V 102 103
Wireless Components
5-6
Specification, 17.02.00
TUA 4401K
Reference
5.2 Phase detector outputs
fr fn
PD_O
Polarity pos.
P-Channel Tri-State. N-Channel
Frequency fn < fr or fV lagging
Frequency fn > fr or fV leading
Frequency fn = fr
Wireless Components
5-7
Specification, 17.02.00
TUA 4401K
Reference
5.3 Bus Interface
1. Bus Interface I2C Bus 2. Bus Data Format I2C Bus Write Mode
MSB
CHIP ADDRESS (WRITE) 1 0 0 1 1 0
LSB
MSB
SUB ADDRESS (WRITE) 00H...07H, 0BH S6 S5 S4 S3 S2 S1
LSB
MSB
DATA IN X...0 (X=7 or 15) ... D5 D4 D3 D2 D1
LSB
STA
1
0
ACK
S7
S0
ACK
DX
D0
ACK
STO
I C Bus Read Mode
MSB
2
CHIP ADDRESS (WRITE) 1 0 0 1 1 0
MSB
LSB
MSB
SUB ADDRESS (READ) 82H/83H 0 0 0 0
LSB R8 ACK1)
LSB
MSB
CHIP ADDRESS (READ) 1 0 0 1
LSB
LSB
STA
1
0
ACK
1
0
1
0
MSB
ACK
STA
1
1
0
1
ACK
DATA OUT FROM SUB ADD 82H
R14 R13 R12 R11 R10 R9
DATA OUT FROM SUB ADD 82H/83H R6 R5 R4 R3 R2 R1
R15
R7
R0
ACK2)
STO
1): mandatory LOW send by uP, 2): mandatory HiGH send by uP
Chipaddress Organisation
Chip Address MSB 1 1 1 1 0 0 0 0 1 1 1 1 0 0 LSB 0 1 Function Chip Address Write Chip Address Read
Subaddress Organisation
Sub Addresses of Data Registers Write MSB Bin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 1 LSB 0 1 0 1 0 1 0 1 1 Hex 00H 01H 02H 03H 04H 05H 06H 07H 0BH Function Status R_Counter N_Counter Mute_DAC7 IF_COUNT_P1 IF_COUNT_P2 Specials Gain_DAC4 COMP-PRESET
Sub Address of Data Register Read MSB Bin LSB Hex Function Result Multipath, Fieldstrength, IF_Window and IF_Center Result-MISC
1
0
0
0
0
0
1
0
82H
1
0
0
0
0
0
1
1
83H
Wireless Components
5-8
Specification, 17.02.00
TUA 4401K
Reference
Data Byte Specification
Status Subaddress 00H Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function not used (must be=0) Port_2 (0=low, 1=high) Port_1 (0=low, 1=high) not used (must be=0) Loopamp current not used (must be=0) not used (must be=0) not used (must be=0) ADC_Single ADC_Mode ADC_ON IF_DAC4 not used (must be=0) CP_Current 2 CP_Current 1 CP_Mode R_Counter Subaddress 01H Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function 215 214 213 2
12
N_Counter Subaddress 02H Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function 215 214 213 2
12
Results Fieldstrength, Multipath and IF counter Subaddress 82H (read address) Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB Function IF_window Multipath_26 Multipath_25 Multipath_24 Multipath_23 Multipath_22 Multipath_21 Multipath_20 IF_center Fieldstrength_26 Fieldstrength_25 Fieldstrength_24 Fieldstrength_23 Fieldstrength_22 Fieldstrength_21 Fieldstrength_20
211 210 2
9
211 210 2
9
28 27 26 2
5
28 27 26 2
5
24 2
3
24 2
3
22 21 20
22 21 20
Mute_DAC7 Subaddress 03H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function
IF_Count_P1 Subaddress 04H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function
IF_Count_P2 Subaddress 05H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function CF_Mod e CF_6 CF_5 CF_4 CF_3 CF_2 CF_1 CF_0
Specials Subaddress 06H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function XTAL_DIV6 VCO_2 AGC_1 AGC_0 XTAL_3 XTAL_2 XTAL_1 XTAL_0
IF_DAC4 Subaddress 07H Bit MSB D7 D6 D5 D4 D3 D2 D1 D0 LSB Function not used not used not used not used GDAC_3 GDAC_2 GDAC_1 GDAC_0
COMP_PRESET Subaddress 0BH Bit MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 Function not used Fieldstrength_26 Fieldstrength_25 Fieldstrength_24 Fieldstrength_23 Fieldstrength_22 Fieldstrength_21 Fieldstrength_20 not used Multipath_2 6 Multipath_2 5 Multipath_2 4 Multipath_2 3 Multipath_2 2 Multipath_2 1 Multipath_2 0
Enable
MDAC_6 MDAC_5 MDAC_4 MDAC_3 MDAC_2 MDAC_1 MDAC_0
Enable
not used Win_2 Win_1 Win_0 Gate_2 Gate_1 Gate_0
Result Misc Subaddress 83H Bit Function MSB D7 D6 D5 D4 D3 D2
D6 D5 D4 D3 D2 D1 D0 LSB
IF_Window
IF_Center Fieldstrength_Comp Multipath_Comp Res Res
Wireless Components
5-9
Specification, 17.02.00
TUA 4401K
Reference
D1 D0 LSB
Res Res
Status, Subaddress 00H MSB D15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 x x 0 0 1 x x 1 1 1 1 0 1 0 1 1 0 0 1 0 1 0 1 0 D14 D13 D12 0 D11 D10 D9 0 0 LSB MSB D8 0 D7 D6 D5 D4 D3 0 D2 D1 LSB D0 Function these bits must be = 0 opendrain Port_2 output = high level opendrain Port_2 output = low level opendrain Port_1 output = high level opendrain Port_1 output = low level Loopamp currentsource high (ILOOPAMP=2.4mA) for high speed tuning Loopamp currentsource low (ILOOPAMP=1.2mA) 7 bit AD Converter enabled for single mode, stop 7 bit AD Converter enabled for single mode start. To restart single mode write the same bits once more. 7 bit AD Converter enabled for continuous mode run. 7 bit AD Converter enabled for single or continuous mode 7 bit AD Converter disabled for single and continuous mode IF_DAC4 enabled (see subaddress 07H) IF_DAC4 disabled (see subaddress 07H) Chargepump current Icp3 = 4mA Chargepump current Icp2 = 2mA Chargepump current Icp1 = 1mA Chargepump current Icp0 = 500uA Chargepump enabled Chargepump disabled
Subaddress 01H, R_Counter and Subaddress 02H, N_Counter MSB D15 1 D14 1 D13 1 D12 D11 1 1 D10 1 D9 1 LSB MSB D8 1 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 LSB D0 1 Function Divider by 65535
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 0 0
1 0 1 1
1 0 1 0
1 1 1 0
1 1 1 1
0 0 1 1
1 0 0 0
0 1 1 0
0 1 0 1
0 1 0 1
0 0 0 1
Divider by 2000 Divider by 1230 Divider by 1000 Divider by 615
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 0 0
1 0 0
0 0 0
0 1 0
1 0 0
0 1 1
0 0 0
Divider by 100 Divider by 10 Divider by 2
Wireless Components
5 - 10
Specification, 17.02.00
TUA 4401K
Reference
Subaddress 03H, Mute_DAC7 MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 Function
Subaddress 05H, IF_Count_P2, Centerfrequency = CF, CFstep= 6.25kHz) / 12.5 kHz MSB D7 1 0 D6 D5 D4 D3 D2 D1 LSB D0 Function Centerfrequency CF1 Centerfrequency CF0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CF1= 22.3875 MHz CF0= 11.1937 MHz
1
1
1
1
1
1
1
1
not used (must be 1)
1 0
Subaddress 04H, IF_Count_P1 MSB D7 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 D6 D5 D4 D3 D2 D1 LSB D0 Function IF_Count enabled IF_Count disabled not used (must be=0) Window=+/-100kHz* Window=+/-50kHz* Window=+/-25kHz* Window=+/-12.5kHz* Window=+/-6.25kHz* Gatetime= 40.96ms Gatetime= 20.48ms Gatetime= 10.24ms Gatetime= 5.12ms Gatetime= 2.56ms Gatetime= 1.28ms Gatetime= 640us Gatetime= 320us 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF1= 20.800 MHz CF0= 10.400 MHz 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 CF1= 21.000 MHz CF0= 10.500 MHz 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 CF1= 21.200 MHz CF0= 10.600 MHz 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 CF1= 21.4125 MHz CF0= 10.70625 MHz CF1= 21.400 MHz CF0= 10.700 MHz CF1= 21.3875 MHz CF0= 10.69375 MHz 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 CF1= 22.600 MHz CF0= 10.800 MHz
* Valid for D7= 0 in subaddress 05H Multiply window value with 2 for D7= 1 in subaddress 05H (e. g. D7= 0 D7= 1 Window =+/- 6.25 kHz Window =+/- 12.5 kHz)
Centerfrequencies for D7=1 D7=0 CF1= 20.800 MHz +n*12.5 kHz, CF Step=12.5 kHz CF0= 10.400 MHz +n*6.25 kHz, CFStep=6.25 kHz n=0...127
Wireless Components
5 - 11
Specification, 17.02.00
TUA 4401K
Reference
Subaddress 06H, Specials MSB D7 1 0 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D6 D5 D4 D3 D2 D1 LSB D0 Function XTAL_DIV6 enabled XTAL_DIV6 disabled 1st LO divided by 1 1st LO divided by 2 Prest. AGC threshold typ. 15 mV Prest. AGC threshold typ. 30 mV Prest. AGC threshold typ. 45 mV Prest. AGC threshold typ. 60 mV XTAL_adjust CL = 15 pF XTAL_adjust CL = 14pF XTAL_adjust CL = 13 pF XTAL_adjust CL = 12 pF XTAL_adjust CL = 11 pF XTAL_adjust CL = 10 pF XTAL_adjust CL = 9 pF *) XTAL_adjust CL = 8 pF *) XTAL_adjust CL = 7 pF XTAL_adjust CL = 6 pF XTAL_adjust CL = 5 pF XTAL_adjust CL = 4 pF XTAL_adjust CL = 3 pF XTAL_adjust CL = 2 pF XTAL_adjust CL = 1pF XTAL_adjust CL = 0pF
Subaddress 07H, IF_DAC4 MSB D7 x D6 x D5 x D4 x 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D3 D2 D1 LSB D0 Function not used IF_DAC Gain adj. typ. 16 dB IF_DAC Gain adj. IF_DAC Gain adj. IF_DAC Gain adj. IF_DAC Gain adj. typ. 21 dB IF_DAC Gain adj. IF_DAC Gain adj. IF_DAC Gain adj. IF_DAC Gain adj. IF_DAC Gain adj. IF_DAC Gain adj. IF_DAC Gain adj. typ. 24 dB IF_DAC Gain adj. IF_DAC Gain adj. IF_DAC Gain adj. IF_DAC Gain adj. typ. 26 dB
*) For continuous tuning characteristic it is recommended to skip steps 8 and 9
Subaddress 0BH, Comp preset MSB D15 X FP26 FP25 FP24 FP23 FP22 FP21 FP20 MP26 MP25 MP24 MP23 MP22 D14 D13 D12 D11 D10 D9 LSB D8 MSB D7 X D6 D5 D4 D3 D2 D1 LSB D0 Function not used Preset value Fieldstrength MP21 MP20 Preset value Multipath
Wireless Components
5 - 12
Specification, 17.02.00
TUA 4401K
Reference
Subaddress 82H, Read results from Fieldstrength, Multipath and IF counter MSB D15 1 D14 D13 D12 D11 D10 D9 LSB MSB D8 D7 1 D6 D5 D4 D3 D2 D1 LSB D0 Function IF_counter result: IF frequency is outside the desired window. IF frequency is lower as the desired IF frequency. IF_counter result: IF frequency is outside the desired window.IF frequency is higher as the desired IF frequency. IF_counter result: IF frequency is inside the desired window Result multipath byte M6...M0 F26 F25 F24 F23 F22 F21 F20 Result fieldstrength byte F6...F0
0
1
x M26 M25 M24 M23 M22 M21 M20
0
Subaddress 83H, Read results misc MSB D7 1 D6 1 D5 D4 D3 Res D2 Res D1 Res LSB D0 Res Function IF_counter result: IF frequency is outside the desired window. IF frequency is lower as the desired IF frequency. IF_counter result: IF frequency is outside the desired window.IF frequency is higher as the desired IF frequency. IF_counter result: IF frequency is inside the desired window Fieldstrength is higher as the preseted value in subaddress 0BH (D8...D14) Fieldstrength is lower as the preseted value in subaddress 0BH (D8...D14) 1 0 Multipathsignal is higher as the preseted value in subaddress 0BH (D0...D6) Multipathsignal signal is lower as the preseted value in subaddress 0BH (D0...D6)
0
1
Res
Res
Res
Res
x
0 1 0
Res
Res
Res
Res
5.4 I2C Bus Timing
BUS_MODE = LOW
tBUF
SDA
tHD.STA tR tLOW tF tSP
SCL
P
tHD.STA
S
tHD.DAT
tHIGH
tSU.DAT
tSU.STA
tSU.STO
S
P
Wireless Components
5 - 13
Specification, 17.02.00
TUA 4401K
Reference
Table 5-4 Parameter LOW level input voltage (SDA, SCL) HIGH level input voltage (SDA, SCL) Pulse width of spikes which must be suppressed by the input filter LOW level output voltage 3mA sink current (SDA) Output fall time from VIHmin to VILmax with a bus capacitance from 10pF to 400pFwith up to 3mA SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set -up time Rise, fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line
2)
Symbol VIL VIH tSP VOL tOF fSCL tBUF tHO.STA tLOW tHIGH tSU.STA tHD.DAT tSU.DAT tR, tF tSU.STO Cb
min -0.5 2.10 0 0 20+0.1Cb2) 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1Cb2) 0.6
max 0.90 5.50 50 0.40 250 400
Unit V V ns V ns kHz s s s s s ns ns
300
ns s
400
pF
Cb= capacitance of one bus line in pF. Note that the maximum tF for the SDA and SCL bus lines quoted at 300ns is longer than the specified maximum tOF for the output stages (250ns).This allows series protection resistors to be connected between the SDA / SCL pins and the SDA /SCL bus lines without exceeding the maximum specified tF.
Wireless Components
5 - 14
Specification, 17.02.00

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